Preface 	ix
Chapter 1 
SDF 	1
	1.1	What is it?, 1
	1.2	The Format, 5
		Delays 12
		Timing Checks 15
		Labels 17
		Timing Environment 17
	1.2.1	Examples, 17
		Full-adder 17
		Decade Counter 24
	1.3	The Annotation Process, 31
	1.3.1	Verilog HDL, 32
	1.3.2	VHDL, 34
	1.4	Mapping Examples, 36
		Propagation Delay 36
		Input Setup Time 40
		Input Hold Time 42
		Input Setup and Hold Time 43
		Input Recovery Time 44
		Input Removal Time 45
		Period 46
		Pulse Width 46
		Input Skew Time 47
		No-change Setup Time 48
		No-change Hold Time 48
		Port Delay 49
		Net Delay 49
		Interconnect Path Delay 50
		Device Delay 50
	1.5	Complete Syntax, 50
Chapter 2 
SPEF 	63
	2.1	Basics, 63
	2.2	Format, 66
	2.3	Complete Syntax, 80
Chapter 3 
LEF 	91
	3.1	Basics, 91
	3.2	Format, 92
	3.3	Complete Syntax, 105
Chapter 4 
DEF 	117
	4.1	Basics, 117
	4.2	Format, 118
	4.3	Complete Syntax, 130
Chapter 5 
PDEF 	139
	5.1	Basics, 139
	5.2	Format, 142
	5.3	Complete Syntax, 155
Chapter 6 
VCD 	163
	6.1	Basics, 163
	6.2	Four State VCD Example, 164
	6.3	Four State VCD Syntax, 169
	6.4	Extended VCD Example, 172
	6.5	Extended VCD Syntax, 177
Bibliography 	181
Index 	183