Contents

Preface 	xi
CHAPTER 1.	Introduction	1
	1.1.	About VHDL	1
	1.2.	Modeling	2
	1.3.	Host environment	4
	1.4.	Syntax overview	5
CHAPTER 2.	Syntax Guide	9
	2.1.	Access type declaration	14
	2.2.	Aggregate	16
	2.3.	Alias declaration	19
	2.4.	Allocator	22
	2.5.	Architecture body	24
	2.6.	Assertion statement	29
	2.7.	Attribute declaration	31
	2.8.	Attribute name	32
	2.9.	Attribute specification	35
	2.10.	Based literal	39
	2.11.	Bit string literal	41
	2.12.	Block statement	42
	2.13.	Case statement	49
	2.14.	Character literal	52
	2.15.	Component declaration	53
	2.16.	Component instantiation statement	56
	2.17.	Concurrent assertion statement	60
	2.18.	Concurrent procedure call statement	62
	2.19.	Concurrent signal assignment statement	64
	2.20.	Concurrent statement	66
	2.21.	Conditional signal assignment statement	67
	2.22.	Configuration declaration	71
	2.23.	Configuration specification	80
	2.24.	Constant declaration	84
	2.25.	Constrained array type declaration	86
	2.26.	Decimal literal	88
	2.27.	Design file	90
	2.28.	Digit	92
	2.29.	Disconnection specification	93
	2.30.	Entity declaration	95
	2.31.	Enumeration literal	100
	2.32.	Enumeration type declaration	102
	2.33.	Exit statement	104
	2.34.	Expression	106
	2.35.	File declaration	111
	2.36.	File type declaration	113
	2.37.	Floating type declaration	115
	2.38.	Function call	117
	2.39.	Generate statement	120
	2.40.	Graphic character	124
	2.41.	Group declaration	125
	2.42.	Group template declaration	127
	2.43.	Identifier	130
	2.44.	If statement	133
	2.45.	Incomplete type declaration	136
	2.46.	Indexed name	137
	2.47.	Integer	139
	2.48.	Integer type declaration	140
	2.49.	Interface constant declaration	142
	2.50.	Interface file declaration	144
	2.51.	Interface signal declaration	145
	2.52.	Interface variable declaration	147
	2.53.	Library clause	149
	2.54.	Literal	150
	2.55.	Loop statement	152
	2.56.	Name	155
	2.57.	Next statement	156
	2.58.	Null statement	158
	2.59.	Package body	159
	2.60.	Package declaration	162
	2.61.	Physical literal	165
	2.62.	Physical type declaration	167
	2.63.	Procedure call statement	169
	2.64.	Process statement	172
	2.65.	Qualified expression	177
	2.66.	Record type declaration	178
	2.67.	Report statement	180
	2.68.	Return statement	181
	2.69.	Selected name	182
	2.70.	Selected signal assignment statement	184
	2.71.	Sequential statement	188
	2.72.	Signal assignment statement	189
	2.73.	Signal declaration	192
	2.74.	Simple expression	195
	2.75.	Slice name	199
	2.76.	String literal	201
	2.77.	Subprogram body	202
	2.78.	Subprogram declaration	208
	2.79.	Subtype declaration	212
	2.80.	Subtype indication	214
	2.81.	Type conversion	217
	2.82.	Type declaration	219
	2.83.	Unconstrained array type declaration	221
	2.84.	Use clause	223
	2.85.	Variable assignment statement	225
	2.86.	Variable declaration	227
	2.87.	Wait statement	229
CHAPTER 3.	Predefined Environment	231
	3.1.	Predefined attributes	231
	3.1.1.	Type attributes	231
	3.1.2.	Array attributes	235
	3.1.3.	Signal attributes	237
	3.1.4.	Named item attributes	240
	3.2.	Package STANDARD	245
	3.3.	Package TEXTIO	248
	3.4.	Reserved words	252
CHAPTER 4.	Changes from VHDL `87	255
	4.1.	VHDL'93 features	255
	4.2.	Portability from VHDL'87	259
Bibliography 	261
Index 	265