Foreword 	xiii
Preface 	xxi
Chapter 1 
Introduction 	1
	1.1	What is SystemC?, 1
	1.2	Why SystemC?, 3
	1.3	Design Methodology, 6
	1.4	Capabilities, 10
	1.5	SystemC RTL, 12
	1.6	Book Organization, 12
	1.7	Exercises, 13
Chapter 2 
Getting Started 	15
	2.1	Basics, 15
	2.2	Another Example, 18
	2.3	Describing Hierarchy, 21
	2.4	Verifying the Functionality, 24
	2.5	Exercises, 30
Chapter 3 
Data Types 	31
	3.1	Value Holders, 31
	3.2	Summary of Types, 33
	3.3	Bit Type, 35
	3.4	Arbitrary Width Bit Type, 36
	3.5	Logic Type, 40
	3.6	Arbitrary Width Logic Type, 43
	3.7	Signed Integer Type, 46
	3.8	Unsigned Integer Type, 49
	3.9	Arbitrary Precision Signed Integer Type, 50
	3.10	Arbitrary Precision Unsigned Integer Type, 51
	3.11	Resolved Types, 52
	3.12	User-defined Data Types, 53
	3.13	Recommended Data Types, 55
	3.14	Exercises, 55
Chapter 4 
Modeling Combinational Logic 	57
	4.1	SC_MODULE, 57
	4.1.1	File Structure, 59
	4.2	An Example, 61
	4.3	Reading and Writing Ports and Signals, 63
	4.4	Logical Operators, 64
	4.5	Arithmetic Operators, 66
	4.5.1	Unsigned Arithmetic, 67
	4.5.2	Signed Arithmetic, 68
	4.6	Relational Operators, 70
	4.7	Vectors and Ranges, 73
	4.7.1	Constant Index, 73
	4.7.2	Non-constant Index, 75
	4.8	If Statement, 78
	4.9	Switch Statement, 81
	4.10	Loops, 85
	4.11	Methods, 87
	4.12	Structures, 91
	4.13	Multiple Processes and Delta Delay, 93
	4.14	Summary, 94
	4.15	Exercises, 95
Chapter 5 
Modeling Synchronous Logic 	97
	5.1	Modeling Flip-flops, 98
	5.2	Multiple Processes, 100
	5.3	Flip-flop with Asynchronous Preset and Clear, 102
	5.4	Flip-flop with Synchronous Preset and Clear, 107
	5.5	Multiple and Multi-phase Clocks, 108
	5.6	Modeling Latches, 111
	5.6.1	If Statement, 111
	5.6.2	Switch Statement, 115
	5.6.3	Avoiding Latches, 116
	5.7	Summary, 119
	5.8	Exercises, 119
Chapter 6 
Miscellaneous Logic 	121
	6.1	Three-state Drivers, 121
	6.2	Multiple Drivers, 127
	6.3	Handling Don't-cares, 130
	6.4	Hierarchy, 132
	6.5	Parameterizing Modules, 140
	6.6	Variable and Signal Assignments, 143
	6.7	Exercises, 145
Chapter 7 
Modeling Examples 	147
	7.1	Parameterizable Register with Three-state Output, 147
	7.2	A Memory Model, 150
	7.3	Modeling an FSM, 152
	7.3.1	Moore FSM, 152
	7.3.2	Mealy FSM, 156
	7.4	Universal Shift Register, 160
	7.5	Counters, 162
	7.5.1	Modulo-N Counter, 162
	7.5.2	Johnson Counter, 165
	7.5.3	Gray Code Up-down Counter, 166
	7.6	Johnson Decoder, 169
	7.7	A Factorial Model, 170
	7.8	Exercises, 172
Chapter 8 
Writing Testbenches 	173
	8.1	Writing a Testbench, 174
	8.2	Simulation Control, 177
	8.2.1	sc_clock, 177
	8.2.2	sc_trace, 178
	8.2.3	sc_start, 179
	8.2.4	sc_stop, 180
	8.2.5	sc_time_stamp, 180
	8.2.6	sc_simulation_time, 180
	8.2.7	sc_cycle and sc_initialize, 180
	8.2.8	sc_time, 181
	8.3	Waveforms, 182
	8.3.1	Arbitrary Waveform, 182
	8.3.2	Complex Repetitive Waveform, 183
	8.3.3	Generating a Derived Clock, 185
	8.3.4	Reading Stimuli from Files, 187
	8.3.5	Reactive Stimuli, 191
	8.4	Monitoring Behavior, 195
	8.4.1	Asserting Valid Behavior, 195
	8.4.2	Dumping Results into a Text File, 197
	8.5	More Examples, 198
	8.5.1	Flip-flop, 198
	8.5.2	Multiplexer with Synchronous Output, 201
	8.5.3	Full Adder, 206
	8.5.4	Cycle-level Simulation, 210
	8.6	Statement Ordering within sc_main, 212
	8.7	Tracing Aggregate Types, 212
	8.8	Exercises, 214
Chapter 9 
Modeling Beyond RTL 	215
	9.1	SC_THREAD Process, 216
	9.2	Dynamic Sensitivity, 219
	9.3	Constructor Arguments, 222
	9.4	More Examples, 227
	9.4.1	Greatest Common Divisor, 227
	9.4.2	Filter, 229
	9.5	Ports, Interfaces and Channels, 230
	9.6	Advanced Topics, 235
	9.6.1	Shared Data Members, 235
	9.6.2	Fixed Point Types, 236
	9.6.3	Module, 237
	9.6.4	Other Methods, 237
	9.7	Simulation Algorithm, 239
	9.8	Exercises, 241
Appendix A 
Runtime Environment 	243
	A.1	Software Installation, 243
	A.2	Compiling your Design, 244
	A.3	Simulating your Design, 246
	A.4	Debugging, 246
Appendix B 
SystemC RTL: A Synthesizable Subset 	249
	B.1	SystemC Features, 250
	B.2	C++ Features, 252
Bibliography 	257
Index 	259