Contents 

Preface	xv
Chapter 1
Introduction	1
	1.1.	What is Verilog HDL?,  1
	1.2.	History,  2
	1.3.	Major Capabilities,  3
	1.4.	Exercises,  5
Chapter 2
A Tutorial	6
	2.1.	A Module,  6
	2.2.	Delays,  8
	2.3.	Describing in Dataflow Style,  9
	2.4.	Describing in Behavioral Style,  11
	2.5.	Describing in Structural Style,  15
	2.6.	Describing in Mixed-design Style,  17
	2.7.	Simulating a Design,  18
	2.8.	Exercises,  23
Chapter 3
Language Elements	25
	3.1.	Identifiers,  25
	3.2.	Comments,  26
	3.3.	Format,  26
	3.4.	System Tasks and Functions,  27
	3.5.	Compiler Directives,  27
	3.5.1.	`define and `undef,  28
	3.5.2.	`ifdef, `ifndef, `else, `elsif and `endif,  29
	3.5.3.	`default_nettype,  29
	3.5.4.	`include,  30
	3.5.5.	`resetall,  30
	3.5.6.	`timescale,  30
	3.5.7.	`unconnected_drive and `nounconnected_drive,  32
	3.5.8.	`celldefine and `endcelldefine,  33
	3.5.9.	`line,  33
	3.6.	Value Set,  33
	3.6.1.	Integers,  34
	Simple Decimal Form,  34
	Base Format Notation,  35
	3.6.2.	Reals,  37
	3.6.3.	Strings,  37
	3.7.	Data Types,  38
	3.7.1.	Net Types,  39
	Wire and Tri Nets,  40
	Wor and Trior Nets,  41
	Wand and Triand Nets,  41
	Trireg Net,  42
	Tri0 and Tri1 Nets,  42
	Supply0 and Supply1 Nets,  43
	3.7.2.	Undeclared Nets,  43
	3.7.3.	Vectored and Scalared Nets,  44
	3.7.4.	Variable Types,  44
	Reg Variable,  45
	Memories,  45
	Integer Variable,  48
	Time Variable,  50
	Real and Realtime Variable,  51
	3.7.5.	Arrays,  51
	3.7.6.	Difference between Reg and Wire,  52
	3.8.	Parameters,  53
	3.8.1.	Local Parameters,  54
	3.9.	Exercises,  54
Chapter 4
Expressions	56
	4.1.	Operands,  56
	4.1.1.	Constant,  57
	4.1.2.	Parameter,  58
	4.1.3.	Net,  58
	4.1.4.	Variable,  59
	4.1.5.	Bit-select,  59
	4.1.6.	Part-select,  60
	4.1.7.	Memory and Array Element,  61
	4.1.8.	Function Call,  62
	4.1.9.	Signedness,  62
	4.2.	Operators,  63
	4.2.1.	Arithmetic Operators,  65
	Result Size,  66
	Unsigned and Signed,  67
	4.2.2.	Relational Operators,  69
	4.2.3.	Equality Operators,  71
	4.2.4.	Logical Operators,  72
	4.2.5.	Bit-wise Operators,  73
	4.2.6.	Reduction Operators,  75
	4.2.7.	Shift Operators,  77
	4.2.8.	Conditional Operator,  78
	4.2.9.	Concatenation and Replication,  79
	4.3.	Kinds of Expressions,  81
	4.4.	Exercises,  82
Chapter 5
Gate-level Modeling	83
	5.1.	The Built-in Primitive Gates,  83
	5.2.	Multiple-input Gates,  84
	5.3.	Multiple-output Gates,  87
	5.4.	Tristate Gates,  88
	5.5.	Pull Gates,  90
	5.6.	MOS Switches,  90
	5.7.	Bidirectional Switches,  93
	5.8.	Gate Delays,  93
	5.8.1.	Min:typ:max Delay Form,  95
	5.9.	Array of Instances,  96
	5.10.	Implicit Nets,  97
	5.11.	A Simple Example,  97
	5.12.	A 2-to-4 Decoder Example,  99
	5.13.	A Master-slave Flip-flop Example,  100
	5.14.	A Parity Circuit,  101
	5.15.	Exercises,  102
Chapter 6
User-Defined Primitives	103
	6.1.	Defining a UDP,  103
	6.2.	Combinational UDP,  104
	6.3.	Sequential UDP,  106
	6.3.1.	Initializing the State Variable,  106
	6.3.2.	Level-sensitive Sequential UDP,  107
	6.3.3.	Edge-triggered Sequential UDP,  107
	6.3.4.	Mixing Edge-triggered and Level-sensitive Behavior,  108
	6.4.	Another Example,  109
	6.5.	Summary of Table Entries,  110
	6.6.	Exercises,  110
Chapter 7
Dataflow Modeling	112
	7.1.	Continuous Assignment,  112
	7.2.	An Example,  115
	7.3.	Net Declaration Assignment,  115
	7.4.	Delays,  116
	7.5.	Net Delays,  118
	7.6.	Examples,  120
	7.6.1.	Master-slave Flip-flop,  120
	7.6.2.	Magnitude Comparator,  120
	7.7.	Exercises,  121
Chapter 8
Behavioral Modeling	122
	8.1.	Procedural Constructs,  122
	8.1.1.	Initial Statement,  123
	8.1.2.	Always Statement,  125
	8.1.3.	In One Module,  128
	8.2.	Timing Controls,  130
	8.2.1.	Delay Control,  130
	8.2.2.	Event Control,  132
	Edge-triggered Event Control,  132
	Level-sensitive Event Control,  135
	8.3.	Block Statement,  136
	8.3.1.	Sequential Block,  137
	8.3.2.	Parallel Block,  138
	8.4.	Procedural Assignments,  141
	8.4.1.	Intra-statement Delay,  142
	8.4.2.	Blocking Procedural Assignment,  144
	8.4.3.	Nonblocking Procedural Assignment,  145
	8.4.4.	Continuous Assignment vs Procedural Assignment,  149
	8.5.	Conditional Statement,  150
	8.6.	Case Statement,  152
	8.6.1.	Don’t-cares in Case,  154
	8.7.	Loop Statement,  155
	8.7.1.	Forever-loop Statement,  155
	8.7.2.	Repeat-loop Statement,  156
	8.7.3.	While-loop Statement,  157
	8.7.4.	For-loop Statement,  157
	8.8.	Procedural Continuous Assignment,  158
	8.8.1.	Assign - deassign,  158
	8.8.2.	Force - release,  160
	8.9.	A Handshake Example,  161
	8.10.	Exercises,  163
Chapter 9
Structural Modeling	166
	9.1.	Module,  166
	9.2.	Ports,  167
	9.2.1.	Parameter Ports,  168
	9.3.	Module Instantiation,  169
	9.3.1.	Unconnected Ports,  171
	9.3.2.	Different Port Lengths,  172
	9.3.3.	Module Parameter Values,  173
	Defparam Statement,  173
	Module Instance Parameter Value Assignment,  174
	9.4.	External Ports,  177
	9.5.	Examples,  182
	9.6.	Generate Statement,  185
	9.6.1.	Generate-loop,  186
	9.6.2.	Generate-conditional,  188
	9.6.3.	Generate-case,  191
	9.7.	Configurations,  192
	9.8.	Exercises,  196
Chapter 10
Other Topics	198
	10.1.	Tasks,  198
	10.1.1.	Task Definition,  198
	10.1.2.	Task Calling,  201
	10.2.	Functions,  204
	10.2.1.	Function Definition,  205
	10.2.2.	Function Call,  208
	10.2.3.	Constant Functions,  209
	10.3.	System Tasks and Functions,  210
	10.3.1.	Display Tasks,  211
	Display and Write Tasks,  211
	Strobe Tasks,  213
	Monitor Tasks,  214
	10.3.2.	File I/O Tasks,  215
	Opening and Closing Files,  215
	Writing out to a File,  217
	Reading from a File,  218
	Annotating from a SDF file,  219
	10.3.3.	Timescale Tasks,  220
	10.3.4.	Simulation Control Tasks,  221
	10.3.5.	Simulation Time Functions,  222
	10.3.6.	Conversion Functions,  223
	10.3.7.	Probabilistic Distribution Functions,  223
	10.3.8.	String Formatting,  225
	10.4.	Disable Statement,  226
	10.5.	Named Events,  228
	10.6.	Mixing Structure with Behavior,  231
	10.7.	Hierarchical Path Name,  232
	10.8.	Sharing Tasks and Functions,  235
	10.9.	Attributes,  237
	10.10.	Value Change Dump (VCD) File,  238
	10.10.1.	Four-state VCD File,  238
	10.10.2.	Extended VCD File,  240
	10.10.3.	An Example,  241
	10.10.4.	Format of VCD File,  243
	10.11.	Specify Block,  243
	10.12.	Strengths,  253
	10.12.1.	Drive Strength,  253
	10.12.2.	Charge Strength,  254
	10.13.	Race Condition,  255
	10.14.	Command Line Arguments,  257
	10.15.	Exercises,  258
Chapter 11
Verification	260
	11.1.	Writing a Test Bench,  260
	11.2.	Waveform Generation,  261
	11.2.1.	A Sequence of Values,  261
	11.2.2.	Repetitive Patterns,  263
	11.3.	Testbench Examples,  270
	11.3.1.	A Decoder,  270
	11.3.2.	A Flip-flop,  271
	11.4.	Reading Vectors from a Text File,  273
	11.5.	Writing Vectors to a Text File,  276
	11.6.	Some More Examples,  277
	11.6.1.	A Clock Divider,  277
	11.6.2.	A Factorial Design,  279
	11.6.3.	A Sequence Detector,  283
	11.6.4.	A LED Sequencer,  285
	11.7.	Utilities,  287
	11.7.1.	Checking for x,  287
	11.7.2.	Passing a File to a Task,  288
	11.7.3.	Debugging Opcodes,  289
	11.7.4.	Check No Missing Clock,  289
	11.7.5.	Clock Burst Generator,  290
	11.8.	Exercises,  291
Chapter 12
Modeling Examples	294
	12.1.	Modeling Simple Elements,  294
	12.2.	Different Styles of Modeling,  299
	12.3.	Modeling Delays,  301
	Transport Delays,  304
	12.4.	Modeling a Truth Table,  305
	12.5.	Modeling Conditional Operations,  307
	12.6.	Modeling Synchronous Logic,  309
	12.7.	A Generic Shift Register,  313
	12.8.	A Gray Counter,  314
	12.9.	A Decade Counter,  315
	12.10.	Parallel to Serial Converter,  316
	12.11.	State Machine Modeling,  316
	12.12.	Interacting State Machines,  319
	12.13.	Modeling a Moore FSM,  323
	12.14.	Modeling a Mealy FSM,  325
	12.15.	A Simplified Blackjack Program,  327
	12.16.	A Scan Cell,  330
	12.17.	A BCD to 7-segment Decoder,  331
	12.18.	Utilities,  332
	12.18.1.	Default Value on a Bus,  332
	12.19.	Exercises,  333
Appendix A
Syntax Reference	335
	A.1.	Keywords,  335
	A.2.	Syntax Conventions,  337
	A.3.	The Syntax,  337
Bibliography	369
Index	370